A resistance change memory such as a ReRAM (resistive RAM) may be formed into a cross point type. Therefore, cell arrays can be easily stacked so that the integration degree can be improved. However, when the number of cell arrays stacked is simply increased, cost increase and yield reduction may be caused. For instance, when a wiring layer is electrically connected to another wiring layer, a via is formed between the wiring layers. The formation of such a via with respect to each layer increases the number of layers, leading to cost increase.
Accordingly, a manufacturing method for forming a via at the same time with respect to wiring layers of a plurality of previously stacked cell arrays has hitherto been proposed. In this method, first, a lower wiring layer, an intermediate wiring layer, and an upper wiring layer are sequentially stacked from below. In that case, a slit is formed in a connecting portion of the intermediate wiring layer to a via. Then, a via from the top of the intermediate wiring layer to the lower wiring layer through the slit is formed. In that case, the via is formed so that steps which engage the connecting portion of the intermediate wiring layer can be made on its side surfaces. Thereby, the lower wiring layer and the intermediate wiring layer can be electrically connected. Further, when the upper wiring layer is formed at the upper end of the via formed in this manner, three wiring layers can be connected by one-time via formation. In other words, according to this method, even when the number of cell arrays stacked is increased, the number of processes of lithography and etching for via formation can be reduced so that cost increase and yield reduction can be suppressed.
However, in this manufacturing method, since the via across the plurality of wirings is formed in the position of the slit formed in the connecting portion of one intermediate wiring layer, an amount of the etching on the connecting portion of the intermediate wiring layer is larger than when the via is formed in each layer. Therefore, the periphery of the slit of the connecting portion of the intermediate wiring layer is removed, with the result that the contact thereof with the via becomes unstable. This becomes more significant as the number of wiring layers stacked between the lower wiring layer and the intermediate wiring layer is larger.